While the present invention will be described with particular reference to application specific integrated circuits (ASICs), the concepts are applicable to field programmable gate arrays (FPGAs) and to configurable logic blocks (CLBs) therein.
Integrated circuits are used in a wide range electronic devices produced by a large number of device manufacturers. In practice, ICs are seldom manufactured (fabricated) by the electronic device manufacturer. Instead, ICs are manufactured by an IC foundry to the specifications of the electronic device manufacturer. More particularly, the IC foundry supplies the technology to fabricate the IC and the device manufacturer supplies the intellectual property incorporated in the circuit of the IC being fabricated. Thus the IC design is often the result of corroboration between the device manufacturer and the IC foundry.
To reduce the time and cost of development of ASICs, IC foundries have developed base IC platforms using semiconductor wafers, sometimes called “slices,” containing layers of semiconductor, such as silicon layers, but without metal interconnection layers. Hardmacs are diffused into the semiconductor layers by permanently embedding transistors and other electronic elements into the wafer layers to achieve specific functions for the ICs. Examples of diffused elements include memories, transceivers, processors, etc. The diffused elements are optimally arranged in groups on the platform that, when properly configured, operate together to perform a particular function, as defined by a macro. The grouping of diffused elements is usually governed by prescribed macro placement rules, with each macro being defined by a plurality of gates and one or more diffused elements. The platform also includes an array composed of pre-diffused transistors, sometimes called the “transistor fabric,” arranged in a grid pattern.
The user selects a platform containing required groups of gates and elements that, when configured to macros, meet the user's requirements for an ASIC. Using tools supplied by the IC manufacturer, the user defines one or more metalization layers that interconnect the diffused elements and associated transistors, thereby creating required macros. These metalization layers also interconnect the transistors to configure them into logical gates. Hence, the user creates the custom ASIC, sometimes called a structured ASIC, by designing the metal interconnect layers to interconnect and configure the macros and gates. The macros do not actually exist on the platform until selected by the user and configured by the metalization layer(s).
There is a wide range of types of ICs. Consequently, foundries provide families of base platforms to perform various functions, with members of the families providing specific sets and arrangements of diffused elements. The user selects a base platform to configure into a custom ASIC best meeting the user's needs. Each platform contains diffused elements at locations so that macros can be created to accommodate the designs for a large number of customers and a large number of different ASICs. The user, using tools supplied by the IC foundry, designs one or more metalization layers for the base platform to interconnect the transistors and diffused elements to create the custom ASIC. In doing so, the user selects groups of diffused elements and associated transistors that form specific macros, creates those macros with the metalization layer, and couples the macros to other logic functions and macros through the metalization layers. Examples of such configurable base platforms are the RapidChip® slices available from LSI Logic Corporation of Milpitas, Calif. The RapidChip slices permit the development of complex, high-density ASICs in minimal time with significantly reduced design and manufacturing risks and costs.
In practice, the user selects a platform that contains the needed elements for necessary macros and whose physical layout is similar to an ideal ASIC for the user's requirements. The user designs the metalization layers to select and create macros and logic gates for the circuit.
Usually, the selected platform also contains elements and gates for macros that are not usable in the completed ASIC design. For example, if the platform contains processor and arithmetic elements and an associated memory element arranged as a potential macro, but the user only requires the memory, the macro was selected for the memory but the arithmetic and processor elements were not used in the completed ASIC. In such a case, the arithmetic and processor elements, along with the associated transistors, remained unused on the chip. Thus the transistor fabric for the macro also was not available for use in the ASIC. As another example, if an ASIC required two macros, such as different processors requiring similar diffused elements, such as similar memories, both groups of elements representing both macros were configured, so that each processor had its own memory.
It is desirable to reduce the number of base platforms in a given family. Each base platform represents a considerable expenditure to design and support. Proliferation of base platforms to meet user requirements adds to the expense of the entire family and the tools to support it. Therefore, it is desirable to design base platforms as generic as practical to reach the requirements of a greater number of users and ASIC designs.